1. Field of the Invention
The present invention relates to a data processor and data processing method for detecting a predetermined mark for synchronous detection included in data and demodulating the data in order to establish the synchronization of a series of the receiving data and particularly to such processor and processing method to execute processes for the data read from various memory media, for example, such as the digital versatile disc (DVD) read only memory (hereinafter referred to as DVD-ROM) and magneto-optical disc (MO) or the like
2. Description of the Related Art
There is provided, for example, a data processor to read (or write) the data from (or to) various kinds of memory media such as DVD or the like. This data processor is provided with a read channel unit and a controller unit to reproduce (or record) the data synchronously with the reference clock signal under the condition that the disc is revolved at the constant number of revolutions as a memory medium. This read channel unit inputs the data read via a read head and also transfers such data to the controller unit.
In these years, on the occasion of transferring the data to the controller unit from this read channel unit, high speed bit rate is required for transferring such data. For example, when it is required to process the data read from a DVD-ROM, the transfer bit rate of about 105 (Mbit/sec) is required in the case of the four-fold data transfer mode. Such a high speed data process is essential for realization of high speed functions of such data processor but, on the other hand, reduction of power consumption is also required because power consumption becomes higher with realization of high speed data processes.
As an example, it is assumed that a pickup head 102 reads the data from a memory medium 101 illustrated in FIG. 17. The data read out from the medium is transferred in synchronization with the clock signal to an LSI 104 for controller as a controller unit from and LSI 103 for read channel as the read channel unit and this data is then processed within an LSI 104 for controller.
Moreover, a controller unit 105 of the data processor as the related art illustrated in FIG. 18 is provided to process the serial data transferred from the read channel unit. The controller unit 105 is provided with a shift register 106, a mark detector 107, a mark-interval counter 108 and a data demodulator 109 which are operating synchronously with the input clock. When the shift register 106 inputs the data in the serial type, the mark detector 107 detects a predetermined mark (for example, data SYn for synchronous signal) to establish the synchronization of data and the mark-interval counter 108 counts the data existing in the interval between the predetermined marks based on the detected predetermined marks. The data demodulator 109 demodulates the data at the demodulation timing based on the counted data.
As illustrated in FIG. 17, in the case where the LSI 103 for read channel and the LSI 104 for controller are formed with individual chips, when the serial data is transferred, for example, in the higher transfer bit rate of 105 (Mbit/sec) to the LSI 104 for controller, a trouble such as data change due to noise or the like is easily generated. Therefore, it is preferable to reduce as much as possible the transfer bit rate between the LSI 103 for read channel and LSI 104 for controller in order to prevent generation of such trouble.
In view of overcoming such trouble, a certain method has been employed to set the condition that the LSI 103 for read channel can transfer the data in a plurality of bit widths in the parallel condition and such preset data can be transferred simultaneously in the parallel condition to the LSI 104 for controller. For example, when the data is transferred simultaneously in the parallel condition with the two-bit width at the time of transferring the serial data in the bit rate of 105 (Mbit/sec), the frequency of clock signal is reduced to a half, namely to 52.5 (MHz) from 105 (MHz). Therefore, the technique to simultaneously transfer the data in the parallel condition with the width of a plurality of bits between the LSI 103 for read channel and LSI 104 for controller is effective for reduction of frequency of the clock signal.
Here, a related art example of the controller unit for processing in parallel the data transferred from the read channel unit will be illustrated in FIG. 19. As illustrated in FIG. 19. the controller unit 110 is provided with a PLL (Phase Locked Loop) circuit 111 for doubling the clock signal synchronized with the data and moreover is also provided with a parallel/serial converting unit 112 for converting the parallel data transferred from the read channel to the serial data, moreover, with addition of the shift register 113, mark detector 114, mark-interval counter 115 and date demodulator 116.
In this case, the PLL circuit 111 doubles the input clock signal and then inputs the data to the shift register 113 after the parallel/serial converting unit 112 that is operating synchronously with the doubled clock signal returns the data to the serial data of the initial condition. The mark detector 114 detects the predetermined mark from the serial data in the shift register 113 and the mark-interval counter 115 counts up the data between the predetermined marks based on the detected predetermined marks. The data demodulator 116 demodulates the data in the demodulation timing based on the counted data.
Here, the predetermined mark detecting method will be explained with reference to FIG. 20. For example, DVD-ROM is used as a memory medium and the data processor illustrated in FIG. 20 detects a pattern of the predetermined marks (data SYn for synchronous signal).
In more practical, the mark detector 119 in the data processor is provided with a memory 119a and a comparator 119b. The memory 119a stores patterns (for example, 12440011h, 12040011h, 92040011h, 92440011h, etc.) of the predetermined marks (data SYn for synchronous signal). The comparator 119b detects whether there is a pattern matched with the pattern (for example, 12440011h or the like) of the predetermined marks (data SYn for synchronous signal) or not from the data inputted to the shift register 118. When it is detected with the comparator 119b that there is a pattern matched with the pattern of the predetermined marks (data SYn for synchronous signal), the comparator 119b outputs a detection signal indicating existence of the predetermined marks (data SYn for synchronous signal) to the mark-interval counter 120.
The mark-interval counter 120 is preset in the timing (namely, in the timing where the detection signal of the data SYn for synchronization signal outputted from the comparator 119b becomes 1) for detecting a pattern of the predetermined marks (data SYn for synchronous data). It is because the mark-interval counter 120 operates with the clock synchronized with the data and requires the timing for detecting the predetermined marks (data SYn for synchronous signal) to measure the data demodulation timing at the time of conducting the count-down from the preset value.
When a method of detecting the predetermined marks is introduced to the controller unit 110 of FIG. 19, there exists a merit that the existing mark detector 114 for synchronous detection, mark-interval counter 115 and data demodulator 116, etc. (refer to FIG. 19) can be used in direct. On the contrary, there exists a demerit, in the case of the controller unit 110, that the PLL circuit 111 for multiplying the clock signal and the parallel/serial converting unit 112 for returning the parallel data to the serial data are newly required in order to process the data simultaneously transferred in the parallel condition with the width of a plurality of bits during operation synchronously with the multiplied clock signal. In the case where the PLL circuit 111 is used, power consumption increases with multiplication of the clock signal, not responding to the requirement for reduction of power consumption.
In the case where the LSI 103 for read channel and LSI 104 for controller illustrated in FIG. 17 are used, if only the process of data is considered, the frequency of the clock signal of the transfer bit rate can be raised up to 400 (MHz) from the existing frequency of about 105 (MHz). However, when the frequency of 400 (MHz) is used, the data synchronizing circuit and demodulating circuit may be designed in the reasonable size of the circuit structure, but these circuits are operated in such frequency, it is rather probable that the power consumption which increases in proportion to the operation rate is considerably shared on the circuit operation.
Moreover, even when the frequency limit is set to about 400 (MHz), here rises a problem that it is impossible to satisfy the requirement of a user for further higher operation rate.